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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16641
SOURCE DRIVER FOR 240-OUTPUT TFT-LCD (64 GRAY SCALES)
DESCRIPTION
The PD16641 is a source driver for TFT-LCD 64 gray scale displays. Its logic circuit operates at 3.3 V and the driver circuit operates at 3.3 or 5.0 V (selectable). The input data is digital data at 6 bits x 3 dots, and 260,000 colors can be displayed in 64-value outputs -corrected by the internal D/A converter and 11 external power supplies. Because the clock frequency is 33 MHzMIN, the PD16641 can be used in TFT-LCD panels conforming to the VGA standards.
FEATURES
* Precharge-less output buffer * 64-value output by 11 external power supplies and internal D/A converter * Level of -corrected power supply can be inverted * Output voltage range: 2.8 VP-PMAX. (at supply voltage VDD2 of driver circuit = 3.0 V) 4.3 VP-PMAX. (at supply voltage VDD2 of driver circuit = 4.5 V) * CMOS level input * 6 bit (gray scale data) x 3 dot input * High-speed data transfer: fmax. = 33 MHzMIN. (internal data transfer rate at supply voltage VDD1 of logic circuit = 3.0 V) * 240 outputs * Supply voltage of driver circuit selectable (Vsel = H: 3.3 V, Vsel = L: 5.0 V) * Slim TCP
ORDERING INFORMATION
Part No. Package TCP (TAB package)
PD16641N-xxx
The TCP is custom-made. For details, consult NEC
Document No. S10565EJ1V0DS00 (1st edition) Date Published May 1998 N CP(K) Printed in Japan
(c)
1998
PD16641
1. BLOCK DIAGRAM
STHR R/L CLK C1 C2 STHL VDD1 (3.3 V) VSS1 C79 C80
80-bit bidirectional shift register
D00 to 05 D10 to 15 D20 to 25
Data register
STB
Latch
Vsel D/A converter V0 to V10
VDD2 (3.3/5.0 V) VSS2
Output buffer
S1
S2
S3
S240
2
PD16641
2. PIN CONFIGURATION (standard TCP: PD16641N-xxx xxx) xxx
COMMON COMMON Vsel VSS2 VDD2 V10 V8 V6 V4 V2 V0 R/L D20 D21 D22 D23 D24 D25 STB STHL VDD1 CLK VSS1 STHR D10 D11 D12 D13 D14 D15 D00 D01 D02 D03 D04 D05 V1 V3 V5 V7 V9 VDD2 VSS2 COMMON
Monitor pin
COMMON COMMON COMMON NC NC NC COMMON COMMON COMMON NC NC NC NC S240 S239
(Copper foil surface)
Monitor pin
S2 S1 NC NC NC NC COMMON COMMON COMMON NC NC NC COMMON COMMON COMMON
Vsel pin is internally pulled up. Therefore, the number of input pins can be reduced by opening or short-circuiting these pins to VSS2 by means of TCP wiring.
3
PD16641
3. PIN DESCRIPTION
Pin Symbol S1 to S240 D00 to D05 D10 to D15 D20 to D25 R/L Shift direction select input This pin inputs/outputs start pulses when two or more PD16641s are connected in cascade. Shift direction of shift register is as follows: R/L = H : STHR input, S1 S240, STHL output R/L = L : STHL input, S240 S1, STHR output R/L = H : Inputs start pulse. R/L = L : Outputs start pulse. R/L = H : Outputs start pulse. R/L = L : Inputs start pulse. Selects driver voltage. This pin is internally pulled up to VDD2. Vsel = VDD2 or OPEN: VDD2 = 3.3 V 0.3 V, Vsel = L: VDD2 = 5.0 V 0.5 V Inputs shift clock to shift register. Display data is loaded to data register at rising edge of this pin. Start pulse output goes high at rising edge of 80th clock after start pulse has been input, and serves as start pulse to driver in next stage. 80th clock of driver in first stage serves as start pulse of driver in next stage. Contents of data register are latched at rising edge, transferred to D/A converter, and output as analog voltage corresponding to display data. Contents of initial shift register are cleared after STB has been input. One pulse of this signal is input when PD16641 is started, and then device operates normally. For STB input timing, refer to Relations between STB, Start Pulse, and Blanking Period in Switching Characteristic Waveform. Inputs -corrected power from external source. VSS2 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 VDD2 VSS2 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 VDD2 Maintain gray scale power supply during gray scale voltage output. 3.3 V 0.3 V Vsel = VDD2 or OPEN : VDD2 = 3.3 V 0.3 V : VDD2 = 5.0 V 0.5 V Vsel = L Ground Ground Pin Name Driver output Display data input Description Output 64 gray scale analog voltages converted from digital signals. Inputs 18-bit-wide display gray scale data (6 bits) x 3 dots (RGB). DX0: LSB, DX5: MSB
STHR
Right shift start pulse I/O
STHL
Left shift start pulse I/O
Vsel
Driver voltage selection
CLK
Shift clock input
STB
Latch input
V0 to V10
-corrected power supply
VDD1 VDD2
Logic circuit power supply Driver circuit power supply
VSS1 VSS2
Logic ground Driver ground
Caution Be sure to turn on power in the order VDD1, logic input, VDD2, and gray scale power (V0 to V10), and turn off power in the reverse order, to prevent the PD16641 from being damaged by latchup. Be sure to observe this power sequence even during a transition period.
4
PD16641
4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The 11 major points on the characteristic curve of the LCD panel are arbitrarily set by external power supplies V0 through V10. If the display data is 00H or 3FH, gray scale voltage V0 or V10 is output. If the display data is in the range 01H to 3EH, the high-order 3 bits select an external powers pair Vn+1, Vn. The low-order 3 bits evenly divide the range of Vn+1 to Vn into eight segments by means of D/A conversion (however, the ranges from V9 to V8 and from V2 to V1 are divided into seven segments) to output a 64 gray scale voltage.
DX5 (MSB) DX4 DX3 DX2 DX1 DX0 (LSB)
High-order 3 bits: -corrected power selected (Vn+1, Vn)
Low-order 3 bits: 3bit D/A (range Vn to Vn+1 is divided into 7 or 8 segments)
DX5 0 0 0 0 1 1 1 1 VDD2
DX4 0 0 1 1 0 0 1 1
DX3 0 1 0 1 0 1 0 1
Vn+1 to Vn V1 to V2 V2 to V3 V3 to V4 V4 to V5 V5 to V6 V6 to V7 V7 to V8 V8 to V9
Vn 1 2 3 4 5 6 7 8 000 001 010 011 100 101 110 111 DX2 to DX0 gray scale supply specified by 00H 7 segments Vn+1
V0 V1 V2
8 segments V3 8 segments V4 8 segments V5 V6 V7 8 segments V8 7 segments V9 8 segments 8 segments
VSS2
V10 0 7 F 17 1F Input data (HEX) 27 2F 37 3F
gray scale supply specified by 3FH
5
PD16641
Relation between Input Data and Output Voltage
Input Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Voltage V0 V2 + (V1 - V2) x 6/7 V2 + (V1 - V2) x 5/7 V2 + (V1 - V2) x 4/7 V2 + (V1 - V2) x 3/7 V2 + (V1 - V2) x 2/7 V2 + (V1 - V2) x 1/7 V2 V3 + (V2 - V3) x 7/8 V3 + (V2 - V3) x 6/8 V3 + (V2 - V3) x 5/8 V3 + (V2 - V3) x 4/8 V3 + (V2 - V3) x 3/8 V3 + (V2 - V3) x 2/8 V3 + (V2 - V3) x 1/8 V3 V4 + (V3 - V4) x 7/8 V4 + (V3 - V4) x 6/8 V4 + (V3 - V4) x 5/8 V4 + (V3 - V4) x 4/8 V4 + (V3 - V4) x 3/8 V4 + (V3 - V4) x 2/8 V4 + (V3 - V4) x 1/8 V4 V5 + (V4 - V5) x 7/8 V5 + (V4 - V5) x 6/8 V5 + (V4 - V5) x 5/8 V5 + (V4 - V5) x 4/8 V5 + (V4 - V5) x 3/8 V5 + (V4 - V5) x 2/8 V5 + (V4 - V5) x 1/8 V5 V6 + (V5 - V6) x 7/8 V6 + (V5 - V6) x 6/8 V6 + (V5 - V6) x 5/8 V6 + (V5 - V6) x 4/8 V6 + (V5 - V6) x 3/8 V6 + (V5 - V6) x 2/8 V6 + (V5 - V6) x 1/8 V6 V7 + (V6 - V7) x 7/8 V7 + (V6 - V7) x 6/8 V7 + (V6 - V7) x 5/8 V7 + (V6 - V7) x 4/8 V7 + (V6 - V7) x 3/8 V7 + (V6 - V7) x 2/8 V7 + (V6 - V7) x 1/8 V7 V8 + (V7 - V8) x 7/8 V8 + (V7 - V8) x 6/8 V8 + (V7 - V8) x 5/8 V8 + (V7 - V8) x 4/8 V8 + (V7 - V8) x 3/8 V8 + (V7 - V8) x 2/8 V8 + (V7 - V8) x 1/8 V8 V9 + (V8 - V9) x 6/7 V9 + (V8 - V9) x 5/7 V9 + (V8 - V9) x 4/7 V9 + (V8 - V9) x 3/7 V9 + (V8 - V9) x 2/7 V9 + (V8 - V9) x 1/7 V9 V10
6
PD16641
-Corrected Power Circuit The reference power supply of the D/A converter consists of a ladder circuit with a total of 64 resistors, and
resistance ri between -corrected power pins differs depending on each pair of -corrected power pins. One pair of
-corrected power pins consists of seven or eight series resistors, and resistance ri in the figure below is indicated
as the sum of the seven of eight resistors. The resistance ratio between the -corrected power pins (ri ratio) is designed to be a value relatively close to the ratio of the -corrected voltages V1 through V9 (gray scale voltages in 8 steps) used in an actual LCD panel. Under ideal conditions where there is no difference between the two, therefore, there is no voltage difference between the voltage of the -corrected power supplies and the gray scale voltages in 8 steps of the resistor ladder circuits of the PD16641, and no current flows into the -corrected power pins V1 through V9. As a result, a voltage follower circuit is not necessary.
-corrected power pin -corrected resistor
PD16641
- + - + - + - + - + - + - + - + - + - + - +
V0
i0 R0 = 1.81 k
V1
i1 R1 = ri = 3.57 k
i=1 7
V2
i2 R2 = ri = 3.12 k
i=1 8
Sum of eight -corrected resistors
V3
i3 R3 = ri = 3.08 k
i=1 8
V4
i4 R4 = ri = 2.90 k
i=1 8
V5
i5 R5 = ri = 2.32 k
i=1 8
V6
i6 R6 = ri = 3.35 k
i=1 8
V7
i7 R7 = ri = 3.23 k
i=1 8
V8
i8 R8 = ri = 4.75 k
i=1 7
V9
i9 R9 = 13.5 k
V10
i10
7
PD16641
Relation between Input Data and Output Data Data format : 1 pixel data (6 bits) x RGB (3 dots) Input width : 18 bits R/L = H (right shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 *** *** S239 D10 to D15 S240 D20 to D25
R/L = L (left shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 *** *** S239 D10 to D15 S240 D20 to D25
5. OPERATION OF OUTPUT BUFFER
The output buffer consists of an operational amplifier circuit that does not perform precharge operation. Therefore, driver output current IVOH1/2 is the charging current to the LCD, and IVOL1/2 is the discharging current. The chip has the driving capability to charge or discharge a liquid load with CL = 80 pF to 3 in less than 10 s.
VDD2
Sn VSS2 Write (IVOL/IVOH) 1 horizontal period Write (IVOL/IVOH)
8
PD16641
6. ELECTRIC SPECIFICATION
Absolute Maximum Ratings (VSS1 = VSS2 = 0 V)
Parameter Supply voltage Supply voltage Input voltage Output voltage Permissible dissipation Operating temperature range Storage temperature range Symbol VDD1 VDD2 VI VO PD TA Tstg. Rating -0.3 to +4.5 -0.3 to +7.0 -0.3 to VDD1, 2 + 0.3 -0.3 to VDD1, 2 + 0.3 150 -10 to +75 -55 to +125 Unit V V V V mW C C
Recommended Operating Range (TA = -10 to +75C, VSS1 = VSS2 = 0 V)
Parameter Logic supply voltage Driver supply voltage Driver supply voltage Symbol VDD1 VDD2 VDD2 V0 to V10 fmax. CL Vsel = H Vsel = L Condition MIN. 3.0 3.0 4.5 VSS2 + 0.1 33 150 TYP. 3.3 3.3 5.0 MAX. 3.6 3.6 5.5 VDD2 - 0.1 Unit V V V V MHz pF
-corrected power
Maximum clock frequency Output load capacitance
9
PD16641
Electrical Characteristics (TA = -10 to +75C, VDD1 = 3.0 to 3.6 V, VDD2 = 3.0 to 3.6 V or 4.5 to 5.5 V, VSS1 = VSS2 = 0 V)
Parameter High-level input voltage Low-level input voltage Input leakage current Symbol VIH VIL IL Condition R/L, CLK, STB, STHR (L), D00-05, D10-15, D20-25 D00-05, D10-15, D20-25 R/L, CLK, STB, STHR (L) Vsel, VDD2 = 5.0 V, Vsel, = 0 V STHR (L), IO = -1.0 mA STHR (L), IO = +1.0 mA VDD1 = 3.3 V, VDD2 = 3.3 V V0 = 3.20 V, V6 = 1.95 V V1 = 3.07 V, V7 = 1.70 V V2 = 2.80 V, V8 = 1.46 V V3 = 2.57 V, V9 = 1.11 V V4 = 2.34 V, V10 = 0.10 V V5 = 2.12 V,Note VDD1 = 3.3 V, VDD2 = 5.0 V V0 = 4.90 V, V6 = 2.96 V V1 = 4.69 V, V7 = 2.58 V V2 = 4.28 V, V8 = 2.20 V V3 = 3.92 V, V9 = 1.66 V V4 = 3.56 V, V10 = 0.1 V V5 = 3.23 V,Note V10 V9 to V1 V0 V10 V9 to V1 V0 250 300 -300 150 -250 10 200 -200 -150 10 40 VDD1 - 0.5 0.5 100 MIN. 0.7VDD1 0 TYP. MAX. VDD1 0.3VDD1 1.0 Unit V V
A
k V V
Pull-up resistor High-level output voltage Low-level output voltage Static current consumption of -corrected power (VDD2 = 3.3 V)
RPU VOH VOL IVn1
250
A A
A A A
Static current consumption of -corrected power (VDD2 = 5.0 V)
IVn2
A
(VX is output voltage of analog output pin S1 to S240. VOUT is the voltage applied to analog output pin S1 to S240.) Note Apply ideal voltage to V1 to V9 that is calculated from internal resistor.
10
PD16641
Electrical Characteristics (TA = -10 to +75C, VDD1 = 3.0 to 3.6 V, VDD2 = 3.0 to 3.6 V or 4.5 to 5.5 V, VSS1 = VSS2 = 0 V)
Parameter Driver output current (VDD2 = 3.3 V) Symbol IVOH1 Condition STB = 3.3 V VOUT = 2.2 V, VX = 3.2 V VDD1 = VDD2 = 3.3 V STB = 3.3 V VOUT = 1.1 V, VX = 0.1 V VDD1 = VDD2 = 3.3 V STB = 5.0 V VOUT = 3.9 V, VX = 4.9 V VDD1 = 3.3 V, VDD2 = 5.0 V STB = 5.0 V VOUT = 1.1 V, VX = 0.1 V VDD1 = 3.3 V, VDD2 = 5.0 V VDD1 = 3.3 V, VDD2 = 3.3 V VOUT = 1.65 VDD1 = 3.3 V, VDD2 = 5.0 V VOUT = 2.50 V Output voltage range Dynamic logic current consumption Dynamic driver current consumption Dynamic driver current consumption VO IDD1 IDD21 IDD22 Input data: 00H to 3FH No load
Note
MIN.
TYP. -0.3
MAX. -0.075
Unit mA
IVOL1
0.075
0.25
mA
Driver output current (VDD2 = 5.0 V)
IVOH2
-0.3
-0.1
mA
IVOL2
0.1
0.25
mA
Output voltage deviation
VO
20 20
25 25
mV
mV
VSS2 + 0.1
VDD2 - 0.1 2.0
V mA mA mA
No load, VDD2 = 3.3 V 0.3 V No load, VDD2 = 5.0 V 0.5 V
Note
5.0 6.5
Note
Note The STB cycle is specified at 31 s and fCLK = 16 MHz. Input data: 1010... (checkerboard pattern) Refers to current consumption per driver when cascades are connected under the assumption of VGA single-sided mounting (8 units).
11
PD16641
Switching Characteristics (TA = -10 to +75C, VDD1 = 3.0 to 3.6 V, VDD2 = 3.0 to 3.6 V or 4.5 to 5.5 V, VSS1 = VSS2 = 0 V, tr = tf = 3.0 ns)
Parameter Start pulse delay time Start pulse delay time Driver output delay time 1 Driver output delay time 2 Driver output delay time 1 Driver output delay time 2 Driver output delay time 1 Driver output delay time 2 Driver output delay time 1 Driver output delay time 2 Input capacitance Input capacitance Input capacitance Symbol tPLH1 tPHL1 tPLH21 tPLH31 tPHL21 tPHL31 tPLH22 tPLH32 tPHL22 tPHL32 CI1 CI2 CI3 V0 to V10, TA = 25C STHR (L), TA = 25C STHR (L), other than V0 to V10 TA = 25C VO: 0.1 V 4.9 V VDD2 = 5.0 V 2 k + 75 pF x 2 VO: 4.9 V 0.1 V CL = 15 pF CL = 15 pF VO: 0.1 V 3.2 V VDD2 = 3.3 V 2 k + 75 pF x 2 VO: 3.2 V 0.1 V Condition MIN. 2.0 2.0 6.0 8.0 6.0 8.0 6.0 8.0 6.0 8.0 100 10 7.0 15 10 TYP. MAX. 17 17 12 14 10 12 10 12 8.0 10 Unit ns ns
s s s s s s s s
pF pF pF
Timing Requirements (TA = -10 to +75C, VDD1 = 3.0 to 3.6 V, VDD2 = 3.0 to 3.6 V or 4.5 to 5.5 V, VSS1 = VSS2 = 0 V, tr = tf = 3.0 ns)
Parameter Clock pulse width Clock low period Clock high period Data setup time Data hold time Start pulse setup time Start pulse hold time Start pulse low period Start pulse rise time STB setup time Data invalid period Final data timing CLK-STB time STB-CLK time Symbol PWCLK PWCLK(L) PWCLK(H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSPL tSPR tSETUP3 tINV tLDT tCLK-STB tSTB-CLK CLK STB or STB or CLK 7.0 7.0 1 1 1 Condition MIN. 22 4.0 4.0 2.0 2.0 2.0 2.0 2 80 TYP. MAX. Unit ns ns ns ns ns ns ns CLK CLK CLK CLK CLK ns ns
12
PD16641
7. SWITCHING CHARACTERISTIC WAVEFORM (R/L = H)
Unless otherwise specified, the input level is VIH = 0.7 VDD1, VIL = 0.3 VDD1.
PWCLK PWCLK (H) PWCLK (L)
The figures in parenthesis indicate R/L = L
tf tr VDD1
CLK
90 % 10 %
90 % 10 % VSS1
tSETUP1
tHOLD1 VDD1
DXX VSS1 tHOLD2
tSPL
tSETUP2
tHOLD2 VDD1
STHR (STHL) VSS1 tSETUP3 STHL (STHR) VSS1 VDD1 STB VIH VSS1 tPHL31/32 tPHL21/22 Sn Targeted output voltage 0.1VDD2 tSPR1/2 tPLH1 tPHL1 VDD1
tPHL31/32 tPHL21/22 Sn
Targeted output voltage (6-bit accuracy)
Targeted output voltage 0.1VDD2
13
PD16641
Switching Characteristic Waveform
tINV VDD1 CLK 1 2 3 4 VSS1 tSETUP2 tHOLD2 VDD1 STHR (STHL) VSS1 tSETUP1 tHOLD1 VDD1 DXX 1 2 3 4 VSS1 tLDT (1 CLKMAX.) 638 639 640 641 642 VDD1 CLK VSS1
VDD1 STB VSS1 tSETUP1 638 639 640 VSS1 tHOLD1 VDD1 DXX
VDD1 CLK VSS1 tCLK-STB tSTB-CLK tCLK-STB tSTB-CLK VDD1 STB VSS1
14
PD16641
8. RELATION BETWEEN STB/STHR, STHL AND BLANKING PERIOD
641 CLK 642 643 644 1 2
DXX (640th Line)
640 tBLK (4 CLKMIN.)
DXX (1st Line) tCLK-STB (7 nsMIN.) tLDT (1 CLKMIN.) tSTB-CLK (7 nsMIN.) tSETUP2 (4 nsMIN.) tHOLD2 (0 nsMIN.)
1
2
STB
VIH VIL tSETUP3 (2 CLKMIN.) VIH VIL
1st STHR (IN)
15
PD16641
9. DATA INPUT TIMING IN CASCADE CONNECTION
78 CLK 79 80 81 82 83 84
1st DXX (IN)
77
78
79
80
1st STHL (OUT) 2nd STHR (IN)
2nd DXX (IN)
1
2
3
CLK
STB
Output
Hi-z
Output
16
PD16641
10. RECOMMENDED MOUNTING CONDITIONS
Mounting this product under the following conditions is recommended. For the mounting methods and conditions other than those recommended, consult NEC.
Mounting Conditions Thermocompression bonding Mounting Method Soldering Conditions Heating tool: 300 to 350C, Heating time: 2 to 3 seconds, Pressure: 100 g (per product) Preliminary adhesion: 70 to 100C, Pressure: 3 to 8 kg/cm , Time: 3 to 5 seconds 2 Real adhesion: 165 to 180C, Pressure: 25 to 45 kg/cm , Time 30 to 40 seconds (when SUMIZAC1003 of Sumitomo Bakelite is used)
2
ACF (sheet adhesive)
Note For the mounting conditions for ACF, consult the ACF manufacturer. Do not use two or more mounting methods in combination. Reference NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades to NEC's Semiconductor Devices (C11531E)
17
PD16641
[MEMO]
18
PD16641
[MEMO]
19
PD16641
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

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